1. Field of the Invention
This invention relates to decoding of prediction-coded video signals, and more particularly is directed to the application of parallel processing to such decoding.
2. Description of Related Art
It is well known to perform compression coding on video data which represents a moving picture in order to reduce the quantity of data to be recorded and/or transmitted. Such data compression may be useful, for example, in recording/reproducing systems using recording media such as magnetic tape or optical disks, and is also useful in transmission systems such as those used for video teleconferencing, video telephone, television broadcasting (including direct satellite broadcast), and the like. For example, it has been proposed by the Moving Picture Experts Group (MPEG) to compression-code moving picture video data utilizing motion-compensated prediction, transform processing using an orthogonal transformation such as the discrete cosine transform (DCT), and variable-length coding. A system for decoding and reproducing such compression-coded video data is illustrated in block diagram form in FIG. 14.
As shown in FIG. 14, a sequence of compression-coded video data is provided at an input terminal 101 for processing, in turn, by an inverse VLC (variable-length coding) circuit 102, an inverse quantization circuit 103, and an inverse DCT circuit 104. An adding circuit 105 forms a reconstructed frame of video data on the basis of a difference signal provided from the inverse DCT circuit 104 and predictive picture data (reference data) provided from a motion compensation circuit 106. The resulting reconstructed video data is stored in a frame memory 107.
The motion compensation circuit 106 forms the predictive picture data from reconstructed data previously stored in frame memory 107 on the basis of motion compensation information (including, for example, motion vectors) extracted from the input signal and supplied to the motion compensation circuit 106 by the inverse VLC circuit 102. Alternatively, with respect to frames for which predictive coding was not performed, such as "intra-frame" coded data, the motion compensation circuit 106 simply provides the value "0" to the adder 105. Reconstructed frames of video data are output from the frame memory 107 via a digital-to-analog converter 108 for display by a display device 109.
As the number of pixels in each frame of the video signal has increased from, for example, the 352.times.240 frame used for video telephone to the 720.times.480 frame used in the NTSC format or the 1920.times.1024 frame in a HDTV (high definition television) system, it was found to be difficult to perform the necessary processing using only one processor and one program execution sequence. For this reason, it has been proposed to divide each frame of the video data into a plurality of subframes, as illustrated in FIG. 16, and then to provide a respective processor for each of the plurality of subframes, so that coding and decoding are performed with parallel processing by the plurality of processors. For example, FIG. 15 is a block diagram of a decoding system provided in accordance with this proposal.
In the system of FIG. 15, input sequences of encoded video data, each representing a respective subframe, are respectively provided via input terminals 110-113 to processors (decoder blocks) 114-117. The processors 114-117 decode the respective data sequences based upon data supplied from frame memories 119-122, which store respective subframes and are assigned to respective ones of the processors 114-117. For example, processor 114 stores a subframe of decoded data in the memory 119. In order to provide motion compensation, a switching logic circuit 118 provided between the processors 114-117 and the frame memories 119-122, permits the processor 114 to read out data from an adjacent portion of the frame memory 120 as well as from all of frame memory 119. The switching logic circuit 118 also provides frames of output video data from the memories 119-120, via a digital-to-analog converter 123 for display on a display device 124.
The four data sequences respectively provided to the processors 114-117 can, for practical purposes, be combined into a single data sequence by providing headers for controlling multiplexing of the data sequence. For this purpose, a separation block (not shown) is provided upstream from the decoder for separating the combined data sequence into the four sequences to be provided to the respective processors. Examples of parallel processing techniques which use division of a video frame into subframes are disclosed in U.S. Pat. No. 5,138,447 and Japanese Patent Application Laid Open No. 139986/1992 (Tokkaihei 4-139986).
As just described, according to the conventional approach, the video frame was generally divided into subframes which were processed in parallel by respective processors. However, when a frame is divided in this manner, there are restrictions on the extent to which the processors can access data that is outside of the processor's respective subframe. Although, as indicated above, a processor can access a region that adjoins its respective subframe, the extent of such access is limited in order to keep the scale of the switching logic circuit 118 from becoming unduly large. As a result, the degree of compression efficiency is reduced, and there are variations in the quality of the reproduced picture at the boundary between the subframes, which may result in visible artifacts at the subframe boundary.
In addition, the processing for compression-coding is carried out completely separately for each of the subframes, which makes it impossible to provide compression-coding on the basis of data blocks in other subframes, a limitation that is not present when the frame is not divided into subframes. Accordingly, the compression coding method must be changed to accommodate the division into subframes, resulting in a lack of compatibility and a loss in compression efficiency.
Furthermore, if header data is added to the data sequence to be recorded or transmitted in order to provide for multiplexing the data sequence into the respective sequences provided to the parallel processors, the additional header data increases the overhead in the recorded data with a corresponding loss of efficiency, and it may also be necessary to change the coding procedure, and so forth.